def do_rust_gen_targets(d):
    wd = d.getVar('RUST_TARGETS_DIR')
    # Order of BUILD, HOST, TARGET is important in case the files overwrite, most specific last
    rust_gen_target(d, 'BUILD', wd, d.getVar('BUILD_ARCH'))
    rust_gen_target(d, 'HOST', wd, d.getVar('HOST_ARCH'))
    rust_gen_target(d, 'TARGET', wd, d.getVar('TARGET_ARCH'))

do_rust_gen_targets(d)

def rust_gen_target(d, thing, wd, arch):
    import json

    build_sys = d.getVar('BUILD_SYS')
    target_sys = d.getVar('TARGET_SYS')

    sys = d.getVar('{}_SYS'.format(thing))
    prefix = d.getVar('{}_PREFIX'.format(thing))
    rustsys = d.getVar('RUST_{}_SYS'.format(thing))
    os = d.getVar('{}_OS'.format(thing))

    abi = None
    cpu = "generic"
    features = ""

    # Need to apply the target tuning consitently, only if the triplet applies to the target
    # and not in the native case
    if sys == target_sys and sys != build_sys:
        abi = d.getVar('ABIEXTENSION')
        cpu = llvm_cpu(d)
        if bb.data.inherits_class('native', d):
            features = ','.join(llvm_features_from_cc_arch(d))
        else:
            features = llvm_features(d) or ""
        # arm and armv7 have different targets in llvm
        if arch == "arm" and target_is_armv7(d):
            arch = 'armv7'

    rust_arch = oe.rust.arch_to_rust_arch(arch)

    if abi:
        arch_abi = "{}-{}".format(rust_arch, abi)
    else:
        arch_abi = rust_arch

    features = features or d.getVarFlag('FEATURES', arch_abi) or ""
    features = features.strip()

    # build tspec
    tspec = {}
    tspec['llvm-target'] = rust_sys_to_llvm_target(rustsys)
    tspec['data-layout'] = d.getVarFlag('DATA_LAYOUT', arch_abi)
    if tspec['data-layout'] is None:
        bb.fatal("No rust target defined for %s" % arch_abi)
    tspec['max-atomic-width'] = int(d.getVarFlag('MAX_ATOMIC_WIDTH', arch_abi))
    tspec['target-pointer-width'] = d.getVarFlag('TARGET_POINTER_WIDTH', arch_abi)
    tspec['target-c-int-width'] = d.getVarFlag('TARGET_C_INT_WIDTH', arch_abi)
    tspec['target-endian'] = d.getVarFlag('TARGET_ENDIAN', arch_abi)
    tspec['arch'] = arch_to_rust_target_arch(rust_arch)
    if "elf" in os:
        tspec['os'] = "none"
    else:
        tspec['os'] = "linux"
    if "musl" in tspec['llvm-target']:
        tspec['env'] = "musl"
    else:
        tspec['env'] = "gnu"
    if "riscv64" in tspec['llvm-target']:
        tspec['llvm-abiname'] = "lp64d"
    if "riscv32" in tspec['llvm-target']:
        tspec['llvm-abiname'] = "ilp32d"
    if "loongarch64" in tspec['llvm-target']:
        tspec['llvm-abiname'] = "lp64d"
    tspec['vendor'] = "unknown"
    tspec['target-family'] = "unix"
    tspec['linker'] = "{}{}gcc".format(d.getVar('CCACHE'), prefix)
    tspec['cpu'] = cpu
    if features != "":
        tspec['features'] = features
    tspec['dynamic-linking'] = True
    tspec['executables'] = True
    tspec['linker-is-gnu'] = True
    tspec['linker-flavor'] = "gcc"
    tspec['has-rpath'] = True
    tspec['position-independent-executables'] = True
    tspec['panic-strategy'] = d.getVar("RUST_PANIC_STRATEGY")

    # write out the target spec json file
    with open(wd + rustsys + '.json', 'w') as f:
        json.dump(tspec, f, indent=4)

# These are accounted for in tmpdir path names so don't need to be in the task sig

def target_is_armv7(d):
    '''Determine if target is armv7'''
    # TUNE_FEATURES may include arm* even if the target is not arm
    # in the case of *-native packages
    if d.getVar('TARGET_ARCH') != 'arm':
        return False

    feat = d.getVar('TUNE_FEATURES')
    feat = frozenset(feat.split())
    mach_overrides = d.getVar('MACHINEOVERRIDES')
    mach_overrides = frozenset(mach_overrides.split(':'))

    v7=frozenset(['armv7a', 'armv7r', 'armv7m', 'armv7ve'])
    if mach_overrides.isdisjoint(v7) and feat.isdisjoint(v7):
        return False
    else:
        return True

def rust_sys_to_llvm_target(sys):
    if sys.startswith('riscv32gc-'):
        return sys.replace('riscv32gc-', 'riscv32-', 1)
    if sys.startswith('riscv64gc-'):
        return sys.replace('riscv64gc-', 'riscv64-', 1)
    return sys

# generates our target CPU value

def llvm_features(d):
    return ','.join(llvm_features_from_tune(d) +
                    llvm_features_from_cc_arch(d) +
                    llvm_features_from_target_fpu(d))

def llvm_features_from_cc_arch(d):
    f = []
    feat = d.getVar('TARGET_CC_ARCH')
    if not feat:
        return []
    feat = frozenset(feat.split())

    if '-mmmx' in feat:
        f.append("+mmx")
    if '-msse' in feat:
        f.append("+sse")
    if '-msse2' in feat:
        f.append("+sse2")
    if '-msse3' in feat:
        f.append("+sse3")
    if '-mssse3' in feat:
        f.append("+ssse3")
    if '-msse4.1' in feat:
        f.append("+sse4.1")
    if '-msse4.2' in feat:
        f.append("+sse4.2")
    if '-msse4a' in feat:
        f.append("+sse4a")
    if '-mavx' in feat:
        f.append("+avx")
    if '-mavx2' in feat:
        f.append("+avx2")

    return f

def llvm_cpu(d):
    cpu = d.getVar('PACKAGE_ARCH')
    target = d.getVar('TRANSLATED_TARGET_ARCH')

    trans = {}
    trans['corei7-64'] = "corei7"
    trans['core2-32'] = "core2"
    trans['x86-64'] = "x86-64"
    trans['i686'] = "i686"
    trans['i586'] = "i586"
    trans['mips64'] = "mips64"
    trans['mips64el'] = "mips64"
    trans['powerpc64le'] = "ppc64le"
    trans['powerpc64'] = "ppc64"
    trans['riscv64'] = "generic-rv64"
    trans['riscv32'] = "generic-rv32"
    trans['loongarch64'] = "la464"

    if target in ["mips", "mipsel", "powerpc"]:
        feat = frozenset(d.getVar('TUNE_FEATURES').split())
        if "mips32r2" in feat:
            trans['mipsel'] = "mips32r2"
            trans['mips'] = "mips32r2"
        elif "mips32" in feat:
            trans['mipsel'] = "mips32"
            trans['mips'] = "mips32"
        elif "ppc7400" in feat:
            trans['powerpc'] = "7400"

    try:
        return trans[cpu]
    except:
        return trans.get(target, "generic")

def arch_to_rust_target_arch(arch):
    if arch == "i586" or arch == "i686":
        return "x86"
    elif arch == "mipsel":
        return "mips"
    elif arch == "mip64sel":
        return "mips64"
    elif arch == "armv7":
        return "arm"
    elif arch == "powerpc64le":
        return "powerpc64"
    elif arch == "riscv32gc":
        return "riscv32"
    elif arch == "riscv64gc":
        return "riscv64"
    else:
        return arch

# Convert a rust target string to a llvm-compatible triplet

def llvm_features_from_target_fpu(d):
    # TARGET_FPU can be hard or soft. +soft-float tell llvm to use soft float
    # ABI. There is no option for hard.

    fpu = d.getVar('TARGET_FPU')
    return ["+soft-float"] if fpu == "soft" else []

def llvm_features_from_tune(d):
    f = []
    feat = d.getVar('TUNE_FEATURES')
    if not feat:
        return []
    feat = frozenset(feat.split())

    mach_overrides = d.getVar('MACHINEOVERRIDES')
    mach_overrides = frozenset(mach_overrides.split(':'))

    if 'vfpv4' in feat:
        f.append("+vfp4")
    elif 'vfpv3' in feat:
        f.append("+vfp3")
    elif 'vfpv3d16' in feat:
        f.append("+vfp3")
        f.append("-d32")
    elif 'vfpv2' in feat or 'vfp' in feat:
        f.append("+vfp2")

    if 'neon' in feat:
        f.append("+neon")
    elif target_is_armv7(d):
        f.append("-neon")

    if 'mips32' in feat:
        f.append("+mips32")

    if 'mips32r2' in feat:
        f.append("+mips32r2")

    if target_is_armv7(d):
        f.append('+v7')

    if ('armv6' in mach_overrides) or ('armv6' in feat):
        f.append("+v6")
    if 'armv5te' in feat:
        f.append("+strict-align")
        f.append("+v5te")
    elif 'armv5' in feat:
        f.append("+strict-align")
        f.append("+v5")

    if ('armv4' in mach_overrides) or ('armv4' in feat):
        f.append("+strict-align")

    if 'dsp' in feat:
        f.append("+dsp")

    if 'thumb' in feat:
        if d.getVar('ARM_THUMB_OPT') == "thumb":
            if target_is_armv7(d):
                f.append('+thumb2')
            f.append("+thumb-mode")

    if 'cortexa5' in feat:
        f.append("+a5")
    if 'cortexa7' in feat:
        f.append("+a7")
    if 'cortexa9' in feat:
        f.append("+a9")
    if 'cortexa15' in feat:
        f.append("+a15")
    if 'cortexa17' in feat:
        f.append("+a17")
    if ('riscv64' in feat) or ('riscv32' in feat):
        f.append("+a,+c,+d,+f,+m")
    return f