Index of /scarthgap/tmp/work-shared/raspberrypi4-64/kernel-source/drivers/accel/habanalabs/include/gaudi2/asic_reg

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[TXT]arc_farm_arc0_acp_eng_regs.h2026-10-16 14:26 16K 
[TXT]arc_farm_arc0_aux_masks.h2026-10-16 14:26 35K 
[TXT]arc_farm_arc0_aux_regs.h2026-10-16 14:26 17K 
[TXT]arc_farm_arc0_dup_eng_axuser_regs.h2026-10-16 14:26 1.7K 
[TXT]arc_farm_arc0_dup_eng_regs.h2026-10-16 14:26 17K 
[TXT]arc_farm_kdma_ctx_axuser_masks.h2026-10-16 14:26 5.6K 
[TXT]arc_farm_kdma_ctx_axuser_regs.h2026-10-16 14:26 1.6K 
[TXT]arc_farm_kdma_ctx_masks.h2026-10-16 14:26 8.7K 
[TXT]arc_farm_kdma_ctx_regs.h2026-10-16 14:26 2.3K 
[TXT]arc_farm_kdma_kdma_cgm_regs.h2026-10-16 14:26 709  
[TXT]arc_farm_kdma_masks.h2026-10-16 14:26 16K 
[TXT]arc_farm_kdma_regs.h2026-10-16 14:26 3.8K 
[TXT]cpu_if_regs.h2026-10-16 14:26 18K 
[TXT]dcore0_dec0_cmd_masks.h2026-10-16 14:26 9.5K 
[TXT]dcore0_dec0_cmd_regs.h2026-10-16 14:26 1.9K 
[TXT]dcore0_edma0_core_ctx_axuser_regs.h2026-10-16 14:26 1.7K 
[TXT]dcore0_edma0_core_ctx_regs.h2026-10-16 14:26 2.5K 
[TXT]dcore0_edma0_core_masks.h2026-10-16 14:26 17K 
[TXT]dcore0_edma0_core_regs.h2026-10-16 14:26 4.1K 
[TXT]dcore0_edma0_qm_arc_aux_regs.h2026-10-16 14:26 18K 
[TXT]dcore0_edma0_qm_axuser_nonsecured_regs.h2026-10-16 14:26 1.8K 
[TXT]dcore0_edma0_qm_cgm_regs.h2026-10-16 14:26 688  
[TXT]dcore0_edma0_qm_masks.h2026-10-16 14:26 51K 
[TXT]dcore0_edma0_qm_regs.h2026-10-16 14:26 28K 
[TXT]dcore0_edma1_core_ctx_axuser_regs.h2026-10-16 14:26 1.7K 
[TXT]dcore0_edma1_qm_axuser_nonsecured_regs.h2026-10-16 14:26 1.8K 
[TXT]dcore0_hmmu0_mmu_masks.h2026-10-16 14:26 13K 
[TXT]dcore0_hmmu0_mmu_regs.h2026-10-16 14:26 6.7K 
[TXT]dcore0_hmmu0_stlb_masks.h2026-10-16 14:26 16K 
[TXT]dcore0_hmmu0_stlb_regs.h2026-10-16 14:26 3.9K 
[TXT]dcore0_mme_acc_regs.h2026-10-16 14:26 1.7K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h2026-10-16 14:26 1.0K 
[TXT]dcore0_mme_ctrl_lo_arch_base_addr_regs.h2026-10-16 14:26 1.1K 
[TXT]dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h2026-10-16 14:26 2.3K 
[TXT]dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h2026-10-16 14:26 1.1K 
[TXT]dcore0_mme_ctrl_lo_arch_tensor_a_regs.h2026-10-16 14:26 2.1K 
[TXT]dcore0_mme_ctrl_lo_arch_tensor_b_regs.h2026-10-16 14:26 2.1K 
[TXT]dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h2026-10-16 14:26 2.2K 
[TXT]dcore0_mme_ctrl_lo_masks.h2026-10-16 14:26 22K 
[TXT]dcore0_mme_ctrl_lo_mme_axuser_regs.h2026-10-16 14:26 1.7K 
[TXT]dcore0_mme_ctrl_lo_regs.h2026-10-16 14:26 4.3K 
[TXT]dcore0_mme_qm_arc_acp_eng_regs.h2026-10-16 14:26 17K 
[TXT]dcore0_mme_qm_arc_aux_regs.h2026-10-16 14:26 18K 
[TXT]dcore0_mme_qm_arc_dup_eng_axuser_regs.h2026-10-16 14:26 1.8K 
[TXT]dcore0_mme_qm_arc_dup_eng_regs.h2026-10-16 14:26 18K 
[TXT]dcore0_mme_qm_axuser_nonsecured_regs.h2026-10-16 14:26 1.8K 
[TXT]dcore0_mme_qm_axuser_secured_regs.h2026-10-16 14:26 1.7K 
[TXT]dcore0_mme_qm_cgm_regs.h2026-10-16 14:26 674  
[TXT]dcore0_mme_qm_regs.h2026-10-16 14:26 27K 
[TXT]dcore0_mme_sbte0_masks.h2026-10-16 14:26 3.4K 
[TXT]dcore0_mme_sbte0_mstr_if_axuser_regs.h2026-10-16 14:26 1.8K 
[TXT]dcore0_mme_wb0_mstr_if_axuser_regs.h2026-10-16 14:26 1.7K 
[TXT]dcore0_rtr0_ctrl_regs.h2026-10-16 14:26 7.9K 
[TXT]dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h2026-10-16 14:26 7.5K 
[TXT]dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h2026-10-16 14:26 6.5K 
[TXT]dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h2026-10-16 14:26 7.5K 
[TXT]dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h2026-10-16 14:26 6.5K 
[TXT]dcore0_sync_mngr_glbl_masks.h2026-10-16 14:26 5.2K 
[TXT]dcore0_sync_mngr_glbl_regs.h2026-10-16 14:26 33K 
[TXT]dcore0_sync_mngr_mstr_if_axuser_masks.h2026-10-16 14:26 6.3K 
[TXT]dcore0_sync_mngr_mstr_if_axuser_regs.h2026-10-16 14:26 1.8K 
[TXT]dcore0_sync_mngr_objs_masks.h2026-10-16 14:26 3.5K 
[TXT]dcore0_sync_mngr_objs_regs.h2026-10-16 14:26 1.2M 
[TXT]dcore0_tpc0_cfg_axuser_regs.h2026-10-16 14:26 1.6K 
[TXT]dcore0_tpc0_cfg_kernel_regs.h2026-10-16 14:26 3.4K 
[TXT]dcore0_tpc0_cfg_kernel_tensor_0_regs.h2026-10-16 14:26 1.9K 
[TXT]dcore0_tpc0_cfg_masks.h2026-10-16 14:26 22K 
[TXT]dcore0_tpc0_cfg_qm_regs.h2026-10-16 14:26 3.2K 
[TXT]dcore0_tpc0_cfg_qm_sync_object_regs.h2026-10-16 14:26 716  
[TXT]dcore0_tpc0_cfg_qm_tensor_0_regs.h2026-10-16 14:26 1.8K 
[TXT]dcore0_tpc0_cfg_regs.h2026-10-16 14:26 5.9K 
[TXT]dcore0_tpc0_cfg_special_regs.h2026-10-16 14:26 5.1K 
[TXT]dcore0_tpc0_eml_busmon_0_regs.h2026-10-16 14:26 4.1K 
[TXT]dcore0_tpc0_eml_etf_regs.h2026-10-16 14:26 2.6K 
[TXT]dcore0_tpc0_eml_funnel_regs.h2026-10-16 14:26 1.8K 
[TXT]dcore0_tpc0_eml_spmu_regs.h2026-10-16 14:26 3.7K 
[TXT]dcore0_tpc0_eml_stm_regs.h2026-10-16 14:26 3.1K 
[TXT]dcore0_tpc0_qm_arc_aux_regs.h2026-10-16 14:26 18K 
[TXT]dcore0_tpc0_qm_axuser_nonsecured_regs.h2026-10-16 14:26 1.8K 
[TXT]dcore0_tpc0_qm_cgm_regs.h2026-10-16 14:26 681  
[TXT]dcore0_tpc0_qm_regs.h2026-10-16 14:26 28K 
[TXT]dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h2026-10-16 14:26 1.8K 
[TXT]dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h2026-10-16 14:26 2.0K 
[TXT]dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h2026-10-16 14:26 1.9K 
[TXT]dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h2026-10-16 14:26 1.9K 
[TXT]dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h2026-10-16 14:26 1.9K 
[TXT]dcore0_vdec0_brdg_ctrl_masks.h2026-10-16 14:26 27K 
[TXT]dcore0_vdec0_brdg_ctrl_regs.h2026-10-16 14:26 7.4K 
[TXT]dcore0_vdec0_ctrl_special_regs.h2026-10-16 14:26 5.3K 
[TXT]dcore1_mme_ctrl_lo_regs.h2026-10-16 14:26 4.3K 
[TXT]dcore1_sync_mngr_glbl_regs.h2026-10-16 14:26 33K 
[TXT]dcore3_mme_ctrl_lo_regs.h2026-10-16 14:26 4.3K 
[TXT]gaudi2_blocks_linux_driver.h2026-10-16 14:26 2.3M 
[TXT]gaudi2_regs.h2026-10-16 14:26 25K 
[TXT]nic0_qm0_cgm_regs.h2026-10-16 14:26 639  
[TXT]nic0_qm0_regs.h2026-10-16 14:26 25K 
[TXT]nic0_qm_arc_aux0_regs.h2026-10-16 14:26 16K 
[TXT]nic0_qpc0_regs.h2026-10-16 14:26 22K 
[TXT]nic0_umr0_0_completion_queue_ci_1_regs.h2026-10-16 14:26 757  
[TXT]nic0_umr0_0_unsecure_doorbell0_regs.h2026-10-16 14:26 893  
[TXT]pcie_aux_regs.h2026-10-16 14:26 6.6K 
[TXT]pcie_dbi_regs.h2026-10-16 14:26 11K 
[TXT]pcie_dec0_cmd_masks.h2026-10-16 14:26 9.2K 
[TXT]pcie_dec0_cmd_regs.h2026-10-16 14:26 1.8K 
[TXT]pcie_vdec0_brdg_ctrl_axuser_dec_regs.h2026-10-16 14:26 1.8K 
[TXT]pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h2026-10-16 14:26 1.9K 
[TXT]pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h2026-10-16 14:26 1.9K 
[TXT]pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h2026-10-16 14:26 1.9K 
[TXT]pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h2026-10-16 14:26 1.9K 
[TXT]pcie_vdec0_brdg_ctrl_masks.h2026-10-16 14:26 27K 
[TXT]pcie_vdec0_brdg_ctrl_regs.h2026-10-16 14:26 7.1K 
[TXT]pcie_vdec0_ctrl_special_regs.h2026-10-16 14:26 5.1K 
[TXT]pcie_wrap_regs.h2026-10-16 14:26 14K 
[TXT]pcie_wrap_special_regs.h2026-10-16 14:26 4.6K 
[TXT]pdma0_core_ctx_axuser_regs.h2026-10-16 14:26 1.5K 
[TXT]pdma0_core_ctx_regs.h2026-10-16 14:26 2.2K 
[TXT]pdma0_core_masks.h2026-10-16 14:26 15K 
[TXT]pdma0_core_regs.h2026-10-16 14:26 3.6K 
[TXT]pdma0_core_special_masks.h2026-10-16 14:26 5.8K 
[TXT]pdma0_qm_arc_aux_regs.h2026-10-16 14:26 16K 
[TXT]pdma0_qm_axuser_nonsecured_regs.h2026-10-16 14:26 1.7K 
[TXT]pdma0_qm_axuser_secured_regs.h2026-10-16 14:26 1.6K 
[TXT]pdma0_qm_cgm_regs.h2026-10-16 14:26 639  
[TXT]pdma0_qm_masks.h2026-10-16 14:26 44K 
[TXT]pdma0_qm_regs.h2026-10-16 14:26 25K 
[TXT]pdma1_core_ctx_axuser_regs.h2026-10-16 14:26 1.5K 
[TXT]pdma1_qm_axuser_nonsecured_regs.h2026-10-16 14:26 1.7K 
[TXT]pmmu_hbw_stlb_masks.h2026-10-16 14:26 15K 
[TXT]pmmu_hbw_stlb_regs.h2026-10-16 14:26 3.7K 
[TXT]pmmu_pif_regs.h2026-10-16 14:26 3.2K 
[TXT]psoc_etr_masks.h2026-10-16 14:26 9.9K 
[TXT]psoc_etr_regs.h2026-10-16 14:26 2.2K 
[TXT]psoc_global_conf_masks.h2026-10-16 14:26 64K 
[TXT]psoc_global_conf_regs.h2026-10-16 14:26 35K 
[TXT]psoc_reset_conf_masks.h2026-10-16 14:26 98K 
[TXT]psoc_reset_conf_regs.h2026-10-16 14:26 27K 
[TXT]psoc_timestamp_regs.h2026-10-16 14:26 1.2K 
[TXT]rot0_desc_regs.h2026-10-16 14:26 3.2K 
[TXT]rot0_masks.h2026-10-16 14:26 9.7K 
[TXT]rot0_qm_arc_aux_regs.h2026-10-16 14:26 16K 
[TXT]rot0_qm_axuser_nonsecured_regs.h2026-10-16 14:26 1.6K 
[TXT]rot0_qm_cgm_regs.h2026-10-16 14:26 632  
[TXT]rot0_qm_regs.h2026-10-16 14:26 24K 
[TXT]rot0_regs.h2026-10-16 14:26 2.1K 
[TXT]xbar_edge_0_regs.h2026-10-16 14:26 4.7K 
[TXT]xbar_mid_0_regs.h2026-10-16 14:26 4.6K 
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